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September 2006 rev 0.5
PCS2I2314ANZ
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Features
* * * * * * * * * * * One input to 14 output Buffer/Driver Supports up to three SDRAM DIMMs Two additional outputs for feedback Serial interface for output control Low skew outputs Up to 133MHz operation Multiple VDD and VSS pins for noise reduction Dedicated OE pin for testing Low EMI outputs 28 Pin SOIC (300-mil) package 3.3V operation
Functional Description
The PCS2I2314ANZ is a 3.3V buffer designed to distribute high-speed clocks in desktop PC applications. The part has 14 outputs, 12 of which can be used to drive up to three SDRAM DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 133MHz, thus making it compatible with Pentium(R)* II processors. The PCS2I2314ANZ can be used in conjunction with the clock synthesizer for a complete Pentium II motherboard solution. The PCS2I2314ANZ also includes a serial interface which can enable or disable each output clock. On power-up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE.
*Pentium is a registered trademark of Intel Corporation.
Block Diagram BUF_IN SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDATA Serial Interface Decoding SCLOCK SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 OE SDRAM13
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.5
Pin Configuration 28- Pin SOIC Package -- Top View
PCS2I2314ANZ
VDD SDRAM0 SDRAM1 VSS VDD SDRAM2 SDRAM3 VSS BUF_IN SDRAM4 SDRAM5 SDRAM12 VDDIICC SDATA
1 2 3 4 5 6 7 8 9 10 11 12 16pi TSSOP 13 14
28 27 26 25 24 23
VDD SDRAM11 SDRAM10 VSS VDD SDRAM9 SDRAM8 VSS OE SDRAM7 SDRAM6 SDRAM13 VSSIIC SCLK
PCS2I2314ANZ
22 21 20 19 18 17 16 15
Pin Description Pins
1, 5, 24, 28 4, 8, 21, 25 13 16 9 20 14 15 2, 3, 6, 7, 10, 11, 18, 19, 22, 23, 26, 27, 12, 17
Name
VDD VSS VDDIIC VSSIIC BUF_IN OE SDATA SCLK SDRAM [0-13]
Type
P P P P I I I/O I O Ground
Description
3.3V Digital voltage supply 3.3V Serial Interface Voltage supply Ground for serial interface Input clock .5V Tolerant Output Enable, three-states outputs when LOW. Internal pull-up to VDD Serial data input, internal pull-up to VDD. 5V Tolerant Serial clock input, internal pull-up to VDD. 5V Tolerant SDRAM Clock Outputs
Device Functionality OE
0 1
SDRAM [0-13]
High-Z 1 x BUF_IN
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved bits should be programmed to "0" or "1". * Serial interface address for the PCS2I2314ANZ is:
PCS2I2314ANZ
Byte 1: SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
27 26 23 22 --19 18
Description
SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved Reserved SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive)
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0:SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Byte 2: SDRAM Active/Inactive Register (1 = Enable, 0 = Disable), Default = Enable Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
11 10 --7 6 3 2
Description
SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Reserved Reserved SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive)
Pin #
17 12 -------
Description
SDRAM13 (Active/Inactive) SDRAM12 (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved
Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value of all the bits is high after chip is powered up.
IIC Byte Flow Byte
1 2 3 4 5 6
Description
IIC Address Command (dummy value, ignored) Byte Count (dummy value, ignored) IIC Data Byte 0 IIC Data Byte 1 IIC Data Byte 2
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Absolute Maximum Ratings Symbol
VDD VIN VBUFIN TSTG TJ TDV
PCS2I2314ANZ
Parameter
Supply Voltage to Ground Potential DC Input Voltage (Except BUF_IN) DC Input Voltage (BUF_IN) Storage Temperature Junction Temperature Static Discharge Voltage (As per JEDEC STD 22- A114-B)
Rating
-0.5 to +7.0 -0.5 to VDD + 0.5 -0.5 to +7.0 -65 to +150 150 2
Unit
V V V
C C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Operating Conditions1 Parameter
VDD TA CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05
Description
Min
3.135 0
Max
3.465 70 30 7 50
Unit
V C pF pF mS
Note: 1. Electrical parameters are guaranteed under the operating conditions specified.
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Electrical Characteristics
(Test condition: All parameters values are valid within the Operating range, unless otherwise stated)
PCS2I2314ANZ
Parameter
VIL VILIIC VIH VOL VOH ICC IOZ IOFF ICC Ii IDD IDD IDD IDD IDD IDD IDDS
Description
Input LOW Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage1 Output HIGH Voltage Quiescent Supply Current High Impedance Output Current Off-State Current (for SCL ,SDATA) Change in Supply Current Input Leakage Supply Current1 Supply Current1 Supply Current Supply Current Supply Current
1 1 1
Test Conditions
Except serial interface pins For serial interface pins only
Min
Typ
Max
0.8 0.7
Unit
V V V V V A A A A A mA mA mA mA mA mA A
2.0 IOL= 25 mA IOH = -36 mA VDD= 3.465V, Vi = VDD or GND, IO =0 VDD= 3.465V, Vi = VDD or GND VDD= 0V, Vi = 0V or 5.5V VDD= 3.135V to 3.465V One Input at VDD-0.6, All other Inputs at VDD or GND VDD= 3.465V or GND (Applicable to all Input Pins) Unloaded outputs, 133 MHz Loaded outputs, 30pF, 133 MHz Unloaded outputs, 100 MHz Loaded outputs, 30pF ,100 MHz Unloaded outputs, 66.67 MHz Loaded outputs, 30pF ,66.67 MHz BUF_IN=VDD or VSS All other inputs at VDD 2.4 50
0.4 100 10 50 500
-5
+5 266 360 200 290 150 185 500
Supply Current1
1
Supply Current
Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production.
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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Switching Characteristics1 Parameter
Fin tD t3 t4 t5 t6 t7 tPLZ, tPHZ tPZL, tPZH tr tf Duty cycle
2,3
PCS2I2314ANZ
Name
Maximum Operating Frequency = t2 / t1 Rising Edge Rate3 Falling Edge Rate3 Output to Output Skew3 SDRAM Buffer LH Prop. Delay SDRAM Buffer Enable Delay
3 3 3 3
Test Conditions
Measured at 1.5V Measured between 0.4V and 2.4V Measured between 2.4V and 0.4V All outputs equally loaded Input edge greater than 1 V/nS Input edge greater than 1 V/nS Input edge greater than 1 V/nS Input edge greater than 1 V/nS CL = 10pF CL = 400pF CL = 10pF CL = 400pF
Min
45.0 1 1
Typ
50.0 2 2 150
Max
133 55.0 4 4 225 3.5 3.5 5 5 250
Unit
MHz % V/nS V/nS pS nS nS nS nS nS nS
1 1 1 1 6 20
2.7 2.7 3 3
SDRAM Buffer HL Prop. Delay SDRAM Buffer Disable Delay Rise Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3 Fall Time for SDATA (Refer Test Circuit for IIC) Refer figure no.3
250
Note: 1. All parameters specified with loaded outputs. 2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS 3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Test Circuit for SDRAM Enable and Disable Times
S1 2 * VDD Open VSS
VDD 500 VI PULSE GENERATOR RT D.U.T 500 VO
CL
TEST t6/t7 tPLZ/tPZL tPHZ/tPZH
S1 Open 2* VDD VSS
Figure 1. Load circuit for Switching times
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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SDRAM Enable and Disable Times
VM = 1.5V VX = VOL +0.3V VY = VOH -0.3V VOH and VOL are the typical Output Voltage drop that occur with the output load
VI OE INPUT GND tPLZ VDD OUTPUT LOW-to-OFF OFF-to-LOW VOL tPHZ VDD OUTPUT HIGH-to-OFF OFF-to-HIGH VSS Outputs enabled Outputs disabled Outputs enabled tPZH tPZL VDD
PCS2I2314ANZ
VM
VM VX
VY VM
Figure 2. 3-State Enable and Disable times
Test Circuit for IIC Rise and Fall Times
VO = 3.3V
RL = 1k
DUT CL = 10pF or CL = 400pF GND
Figure 3. Test Circuit for IIC
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Switching Waveforms Duty Cycle Timing
t1 t2
1.5 V 1.5 V 1.5 V
PCS2I2314ANZ
All Outputs Rise/Fall Time
2.4 V
OUTPUT
0.4 V
2.4 V 0.4 V
3.3 V 0V
t3
t4
Output - Output Skew
1.5 V
OUTPUT
1.5 V
OUTPUT
t5
SDRAM Buffer LH and HL Propagation Delay
INPUT
OUTPUT
t6
t7
Test Circuit
+3.3V TEST CIRCUIT VDD +3.3V 0.1uF CLKOUT OUTPUT VDD 0.1uF GND GND CLOAD
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
PCS2I2314ANZ
Application Circuit
Rs CPUCLK BUF_IN Rs SDRAM (0.13) SDRAM (0.13)
SDATA SCLK VDD 3.3V
SDATA Ct SCLK
VDD VSS Cd = 0.1 F PCS2I2314ANZ 28-Pin SOIC
Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EMI-REDUCING CAPACITORS Rs = SERIES TERMINATING RESISTORS
Summary
* * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1F. In some cases, smaller value capacitors may be required. The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout * * * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7pF to 22pF. A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. If a Ferrite Bead is used, a 10F-22F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
IIC Serial Interface Information
The information in this section assumes familiarity with IIC programming.
PCS2I2314ANZ
How to program PCS2I2314ANZ through IIC:
* * * * * * * * * * * * * * Master (host) sends a start bit. Master (host) sends the write address D3(H). PCS2I2314ANZ device will acknowledge. Master (host) sends the Command Byte. PCS2I2314ANZ device will acknowledge the Command Byte. Master (host) sends a Byte count PCS2I2314ANZ device will acknowledge the Byte count. Master (host) sends the Byte 0 PCS2I2314ANZ device will acknowledge Byte 0 Master (host) sends the Byte 1 PCS2I2314ANZ device will acknowledge Byte 1 Master (host) sends the Byte 2 PCS2I2314ANZ device will acknowledge Byte 2 Master (host) sends a Stop bit.
Controller (Host)
Start Bit Slave Address D3(H)
PCS22314ANZ (slave/receiver)
ACK Command Byte ACK Byte count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Stop Bit
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Package Information 28L SOIC (300 mil)
PCS2I2314ANZ
Dimensions Symbol
A A1 A2 D h E H R1 b b1 c c1 L e
Inches Min Max
0.093 0.004 0.088 0.697 0.010 0.291 0.394 0.003 0.013 0.013 0.009 0.009 0.016 0 0.104 0.012 0.094 0.712 0.029 0.299 0.419 .... 0.022 0.020 0.015 0.013 0.050 8
Millimeters Min Max
2.35 0.10 2.25 17.70 0.25 7.40 10.00 0.08 0.33 0.33 0.23 0.23 0.40 0 2.65 0.30... 2.40 18.10 0.75 7.60 10.65 ..... 0.56 0.51 0.38 0.33 1.27 8
0.050 BSC
1.27 BSC
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
Ordering Information Ordering Code
PCS2P2314ANZG-28-ST PCS2P2314ANZG-28-SR PCS2I2314ANZG-28-ST PCS2I2314ANZG-28-SR
PCS2I2314ANZ
Marking
2P2314ANZG 2P2314ANZG 2I2314ANZG 2I2314ANZG
Package Type
28 Pin SOIC, Tube, Green 28 Pin SOIC, Tape and Reel, Green 28 Pin SOIC, Tube, Green 28 Pin SOIC, Tape and Reel, Green
Operating Range
Commercial Commercial Industrial Industrial
Device Ordering Information
PCS2I2314ANZG-28-SR
R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70
G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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September 2006 rev 0.5
PCS2I2314ANZ
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2I2314ANZ Document Version: 0.5
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
14 Output, 3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs
Notice: The information in this document is subject to change without notice.
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